Floating-point instructions have a much longer latency than integer instructions. This creates a problem because certain floating-point exceptions can only occur after the instruction has completed. If an unmasked exception is generated by a floating-point instruction, a fault must occur immediately before the next "wait" instruction or non-control type floating-point instruction. Because of the pipelined implementation of some floating-point units (FPUs), and because instructions can be executed in parallel with other instructions in a superscalar machine, the next instruction might already have been executed. Thus, by the time the exception were known, it would be too late to signal a fault. To avoid this situation, safe instruction recognition (SIR) may be implemented in the FPU. SIR works on the premise that safe instructions (instructions that do not have to jump to the internal micro-code exception handler to complete) can be recognized quickly and easily before the entire operation has completed. If an instruction is unsafe, that means it might, or might not cause an internal exception. This final determination can only be made after the operation has completed. If an instruction is unsafe, then the pipeline must be stalled until this final determination can be made. However, if the instruction is found to be safe (which is the usual case) then no stall is needed and the full performance of the pipeline is realized.
The present invention provides for the rapid and efficient detection of unsafe conditions that could lead to abnormal operation of the floating-point processor when executing add, subtract, multiply or divide operations.